1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device including a step of exposing a fine pattern with precise alignment, and an apparatus of automatically adjusting a semiconductor exposure pattern for use in the method.
2. Description of Related Art
In semiconductor devices such as so-called integrated circuits, a finer pattern and a higher integration degree are recently required in association with a larger capacity of memory or a larger number of functions of logics in a CPU (Central Processing Unit). In addition to the integrated circuits, a finer pattern and a higher integration degree are similarly required, for example in imaging devices such as CADS (Charge Coupled Device), as a type of the semiconductor devices by making good use of a fine pattern forming technique which has been developed in the integrated circuits.
In the semiconductor devices such as the integrated circuits, an exposure step was typically performed with a step & repeat method using a so-called stepper exposure unit before a generation in which a 0.25 μm design rule is applied. In a generation in which a 0.25 to 0.18 μm design rule is applied or in a later generation, however, a single manufacturing process for a semiconductor device has employed both an exposure step with the step & repeat method and an exposure step with a scan method using a so-called scanner exposure unit (also referred to as “a scan exposure unit”).
The exposure step in the step & repeat method involves the use of a reticule having a mask pattern formed thereon at a predetermined scaling factor such as 5 times or 10 times in some cases for performing an exposure step to scale down the pattern onto a semiconductor wafer at a predetermined scaling factor. While this exposure step has an advantage of high throughput, it does not necessarily function well for the exposure process of a pattern with a line width design rule of less than 0.25 μm because of limits of resolution or difficulty in making fine adjustments of the pattern during the exposure process.
On the other hand, in the exposure step in the scan method, an exposure step of one mask pattern for one chip involves irradiating an elongated slit area with light and scanning the entire mask pattern through the slit area to perform an exposure step of the entire shot. Since this exposure step allows precise exposure of a very fine pattern with high resolution and permits many parameters for shape correction with a higher degree of freedom, fine adjustments of patterns can be made during the exposure step. In this exposure step, however, both stages of a reticule and a wafer must be controlled simultaneously and thus equipment therefore becomes complicated to cause a higher process cost than the step & repeat method.
To address this, it is becoming popular practice to employ such scan method to perform the exposure in a device pattern forming step which strongly requires precise formation of a fine pattern of less than 0.25 μm such as each structural part of a device or a wiring pattern on the one hand, and on the other hand, to employ the step & repeat method to perform an exposure step in a step of forming a so-called rough-layer pattern with a relatively low fineness of 0.25 μm or more, for example a resist pattern for use in an ion implantation step.
Typically, since the step of forming a pattern of a rough-layer or the like is performed after the device pattern forming step, the exposure step in the step & repeat method is performed after the exposure step by the scan method.
The exposure step in the step & repeat method, however, allows only scale-up/scale-down and parallel shifts over the entire exposure area with regard to adjustments of the shape or a position of a pattern, so that it has a lower degree of freedom than the exposure step in the scan method. Thus, if an offset occurs in the shape or the position of the pattern in the exposure step of the scan method performed earlier, a problem arises in that the existing offset cannot be corrected precisely in some cases in the exposure step of the step & repeat method performed later.
For example, if the exposure step in the scan method results in distortion in an aspect ratio over the entire exposure area, the exposure step with the step & repeat method performed thereafter cannot adjust the dimensions independently in the vertical and horizontal directions over the entire exposure area. For this reason, if adjustments are made to correct the offset only in one of the directions, the offset in the other direction may remain uncorrected or the amount of the offset may increase.
Alternatively, it is contemplated that an effective approach is to prevent occurrence of an offset in the shape or a position in a pattern in the exposure step in the scan method. To realize the approach, however, it is necessary to add a step of forming a marking for indicating a reference point of alignment in the exposure step by the scan method on a wafer to be patterned prior to the exposure step in the scan method since the exposure step in the scan method is typically performed earlier. The necessity causes an additional disadvantage of more complicated manufacturing steps or a lower throughput.